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ltc6406 1 6406fc features applications description 3ghz, low noise, rail-to-rail input differential ampli er/driver the ltc ? 6406 is a very low noise, low distortion, fully differential input/output ampli? er optimized for 3v, single supply operation. the ltc6406 input common mode range is rail-to-rail, while the output common mode voltage is independently adjustable by applying a voltage on the v ocm pin. this makes the ltc6406 ideal for level-shifting signals with a wide common mode range for driving 12-bit to 16-bit single supply, differential input adcs. a 3ghz gain-bandwidth product results in 70db linearity for 50mhz input signals. the ltc6406 is unity-gain stable and the closed-loop bandwidth extends from dc to 800mhz. the output voltage swing extends from near ground to 2v, to be compatible with a wide range of adc converter input requirements. the ltc6406 draws only 18ma, and has a hardware shutdown feature which reduces current consumption to 300a. the ltc6406 is available in a compact 3mm 3mm 16-pin leadless qfn package as well as an 8-lead msop package, and operates over a C40c to 85c temperature range. adc driver: single-ended input to differential output with common mode level shifting n low noise: 1.6nv/ hz rti n low power: 18ma at 3v n low distortion (hd2/hd3): C80dbc/C69dbc at 50mhz, 2v p-p C104dbc/C90dbc at 20mhz, 2v p-p n rail-to-rail differential input n 2.7v to 3.5v supply voltage range n fully differential input and output n adjustable output common mode voltage n 800mhz C3db bandwidth with a v = 1 n gain-bandwidth product: 3ghz n low power shutdown n available in 8-lead msop and tiny 16-lead 3mm 3mm 0.75mm qfn packages n differential input adc driver n single-ended to differential conversion n level-shifting ground-referenced signals n level-shifting v cc -referenced signals n high linearity direct conversion receivers harmonic distortion vs frequency typical application + C C + 150 1.8pf ltc6406 v ocm 1.25v v in 150 150 150 6406 ta01 +ina Cina ltc22xx adc gnd v dd 3v 3v 1.8pf frequency (mhz) 6406 ta01b distortion (dbc) v s = 3v v ocm = v icm = 1.25v r load = 800 v outdiff = 2v p-p differential inputs C30 C40 C50 C60 C70 C80 C90 C110 C100 2nd, r i = r f = 150 2nd, r i = r f = 500 3rd, r i = r f = 150 3rd, r i = r f = 500 1 100 10 l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc6406 2 6406fc absolute maximum ratings total supply voltage (v + to v C ) ................................3.5v input current +in, Cin, v ocm , shdn , v tip (note 2) ...............10ma output short-circuit duration (note 3) ............ inde? nite (note 1) lead free finish tape and reel part marking* package description specified temperature range ltc6406cud#pbf ltc6406cud#trpbf lctc 16-lead (3mm 3mm) plastic qfn 0c to 70c ltc6406iud#pbf ltc6406iud#trpbf lctc 16-lead (3mm 3mm) plastic qfn C40c to 85c ltc6406cms8e#pbf ltc6406cms8e#trpbf ltctb 8-lead plastic msop 0c to 70c ltc6406ims8e#pbf ltc6406ims8e#trpbf ltctb 8-lead plastic msop C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information 16 17 15 14 13 5 6 7 8 top view ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1 shdn v + v C v ocm v C v + v + v C nc +in Cout Coutf v tip Cin +out +outf t jmax = 150c, ja = 68c/w, jc = 4.2c/w exposed pad (pin 17) is v C , must be soldered to pcb 1 2 3 4 top view ms8e package 8-lead plastic msop 1 2 3 4 Cin v ocm v + +out 8 7 6 5 +in shdn v C Cout 9 t jmax = 150c, ja = 40c/w, jc = 10c/w exposed pad (pin 9) is v C , must be soldered to pcb pin configuration operating temperature range (note 4) .... C40c to 85c speci? ed temperature range (note 5) .... C40c to 85c junction temperature ........................................... 150c storage temperature range ................... C65c to 150c
ltc6406 3 6406fc dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v cm = v ocm = v icm = 1.25v, v shdn = open, r bal = 100k , r i = 150 , r f = 150 (0.1% resistors), c f = 1.8pf (see figure 1) unless otherwise noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v icm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). symbol parameter conditions min typ max units v osdiff differential offset voltage (input referred) v icm = 3v (note 12) v icm = 1.25v v icm = 0v (note 12) l l l 1 0.25 1 5 3.5 5 mv mv mv v osdiff / t differential offset voltage drift (input referred) v icm = 3v (note 12) v icm = 1.25v v icm = 0v (note 12) l l l 12 1 7 v/c v/c v/c i b input bias current (note 6) v icm = 3v v icm = 1.25v v icm = 0v l C24 6 C9 C17 C1 a a a i os input offset current (note 6) v icm = 3v v icm = 1.25v v icm = 0v l 1 1 1 3 a a a r in input resistance common mode differential mode 130 3 k k c in input capacitance differential 1 pf e n differential input referred noise voltage density f = 1mhz, not including r i /r f noise 1.6 nv/ hz i n input noise current density f = 1mhz, not including r i /r f noise 2.5 pa/ hz e nvocm input referred common mode output noise voltage density f = 1mhz 9 nv/ hz v icmr (note 7) input signal common mode range op amp inputs l v C v + v cmrri (note 8) input common mode rejection ratio (input referred) v icm / v osdiff v icm from 0v to 3v l 50 65 db cmrrio (note 8) output common mode rejection ratio (input referred) v ocm / v osdiff v ocm from 0.5v to 2v l 50 70 db psrr (note 9) differential power supply rejection ( v s / v osdiff ) v s = 2.7v to 3.5v l 55 75 db psrrcm (note 9) output common mode power supply rejection ( v s / v oscm ) v s = 2.7v to 3.5v l 55 65 db g cm common mode gain ( v outcm / v ocm ) v ocm from 0.5v to 2v l 1v/v g cm common mode gain error 100 ? (g cm C 1) v ocm from 0.5v to 2v l 0.4 0.8 % bal output balance ( v outcm / v outdiff ) v outdiff = 2v single-ended input differential input l l C57 C65 C45 C45 db db v oscm common mode offset voltage (v outcm C v ocm ) l 6 15 mv v oscm / t common mode offset voltage drift l 15 v/c v outcmr (note 7) output signal common mode range (voltage range for the v ocm pin) l 0.5 2 v r invocm input resistance, v ocm pin l 12 18 24 k v ocm self-biased voltage at the v ocm pin v ocm = open l 1.15 1.25 1.35 v v out output voltage, high, +out/Cout pins v s = 3.3v, i l = 0 v s = 3.3v, i l = C20ma l l 2.2 2 2.35 2.15 v v v s = 3v, i l = 0 v s = 3v, i l = C5ma v s = 3v, i l = C20ma l l l 2 1.95 1.7 2.05 2 1.85 v v v output voltage, low, +out/Cout pins v s = 3v, i l = 0 v s = 3v, i l = 5ma v s = 3v, i l = 20ma l l l 0.23 0.34 0.75 0.33 0.4 0.85 v v v
ltc6406 4 6406fc dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v cm = v ocm = v icm = 1.25v, v shdn = open, r bal = 100k , r i = 150 , r f = 150 (0.1% resistors), c f = 1.8pf (see figure 1) unless otherwise noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v icm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). symbol parameter conditions min typ max units i sc output short-circuit current, +out/Cout pins (note 10) l 35 55 ma a vol large-signal open loop voltage gain 90 db v s supply voltage range l 2.7 3.5 v i s supply current l 18 22 ma i shdn supply current in shutdown v shdn = 0v l 300 500 a r shdn shdn pull-up resistor v shdn = 0v to 0.5v l 60 100 140 k v il shdn input logic low l 0.4 0.7 v v ih shdn input logic high l 2.25 2.55 v t on turn-on time 200 ns t off turn-off time 50 ns ac electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v cm = v ocm = v icm = 1.25v, v shdn = open, r i = 150 , r f = 150 (0.1% resistors), c f = 1.8pf, r load = 400 (see figure 2) unless otherwise noted. v s is de? ned as (v + C v C ). v icm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). symbol parameter conditions min typ max units sr slew rate differential output 630 v/s gbw gain-bandwidth product f test = 30mhz 3 ghz f C3db C3db frequency (see figure 2) l 500 800 mhz 50mhz distortion differential input, v outdiff = 2v p-p (note 13) v ocm = 1.25v, v s = 3v 2nd harmonic 3rd harmonic l C77 C65 C55 dbc dbc v ocm = 1.25v, v s = 3v, r load = 800 2nd harmonic 3rd harmonic C85 C72 dbc dbc v ocm = 1.25v, v s = 3v, r load = 800 , r i = r f = 500 2nd harmonic 3rd harmonic C80 C69 dbc dbc 50mhz distortion single-ended input, v outdiff = 2v p-p (note 13) v ocm = 1.25v, v s = 3v, r load = 800 , r i = r f = 500 2nd harmonic 3rd harmonic C69 C73 dbc dbc 3rd-order imd at 49.5mhz, 50.5mhz v outdiff = 2v p-p envelope, r load = 800 C65 dbc oip3 at 50mhz (note 11) r load = 800 36.5 dbm t s settling time v outdiff = 2v step 1% settling 0.1% settling 7 11 ns ns nf noise figure at 50mhz shunt-terminated to 50 , r s = 50 z in = 200 (r i = 100, r f = 300) 14.1 7.5 db db
ltc6406 5 6406fc electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: input pins (+in, Cin, v ocm , shdn and v tip ) are protected by steering diodes to either supply. if the inputs should exceed either supply voltage, the input current should be limited to less than 10ma. in addition, the inputs +in, Cin are protected by a pair of back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. long-term application of output currents in excess of the absolute maximum ratings may impair the life of the device. note 4: the ltc6406c/ltc6406i are guaranteed functional over the operating temperature range C40c to 85c. note 5: the ltc6406c is guaranteed to meet speci? ed performance from 0c to 70c. the ltc6406c is designed, characterized, and expected to meet speci? ed performance from C40c to 85c but is not tested or qa sampled at these temperatures. the ltc6406i is guaranteed to meet speci? ed performance from C40c to 85c. note 6: input bias current is de? ned as the average of the input currents ? owing into the inputs (Cin, and +in). input offset current is de? ned as the difference between the input currents (i os = i b + C i b C ). note 7: input common mode range is tested using the test circuit of figure 1 by taking three measurements of differential gain with a 1v dc differential output with v icm = 0v; v icm = 1.25v; v icm = 3v, verifying that the differential gain has not deviated from the v icm = 1.25v case by more than 0.5%, and that the common mode offset (v oscm ) has not deviated from the common mode offset at v icm = 1.25v by more than 20mv. the voltage range for the output common mode range is tested using the test circuit of figure 1 by applying a voltage on the v ocm pin and testing at both v ocm = 1.25v and at the electrical characteristics table limits to verify that the common mode offset (v oscm ) has not deviated by more than 10mv from the v ocm = 1.25v case. note 8: input cmrr is de? ned as the ratio of the change in the input common mode voltage at the pins +in or Cin to the change in differential input referred voltage offset. output cmrr is de? ned as the ratio of the change in the voltage at the v ocm pin to the change in differential input referred voltage offset. this speci? cation is strongly dependent on feedback ratio matching between the two outputs and their respective inputs, and it is dif? cult to measure actual ampli? er performance (see the effects of resistor pair mismatch in the applications information section of this data sheet). for a better indicator of actual ampli? er performance independent of feedback component matching, refer to the psrr speci? cation. note 9: differential power supply rejection (psrr) is de? ned as the ratio of the change in supply voltage to the change in differential input referred voltage offset. common mode power supply rejection (psrrcm) is de? ned as the ratio of the change in supply voltage to the change in the common mode offset, v outcm C v ocm . note 10: extended operation with the output shorted may cause the junction temperature to exceed the 150c limit. note 11: because the ltc6406 is a feedback ampli? er with low output impedance, a resistive load is not required when driving an adc. therefore, typical output power can be very small in many applications. in order to compare the ltc6406 with rf style ampli? ers that require 50 load, the output voltage swing is converted to dbm as if the outputs were driving a 50 load. for example, 2v p-p output swing is equal to 10dbm using this convention. note 12: includes offset/drift induced by feedback resistors mismatch. see the applications information section for more details. note 13: qfn package only. refer to data sheet curves for msop package numbers. typical performance characteristics differential input referred offset voltage vs temperature differential input referred offset voltage vs input common mode voltage common mode offset voltage vs temperature temperature (c) 6406 g01 differential v os (mv) v s = 3v v ocm = 1.25v v icm = 1.25v r i = r f = 150 five typical units C50 50 100 C25 0 25 75 1.2 1.0 0.8 0.6 0.4 0.2 0 C0.2 input common mode voltage (v) 6406 g02 differential v os (mv) v s = 3v v ocm = 1.25v r i = r f = 150 0.1% feedback network resistors typical unit 0 2.0 3.0 0.5 1.0 1.5 2.5 2.0 1.5 1.0 0.5 C0.5 0 C1.0 C1.5 C2.0 t a = C40c t a = 0c t a = 25c t a = 70c t a = 85c temperature (c) 6406 g03 common mode offset voltage (mv) v s = 3v v ocm = 1.25v v icm = 1.25v five typical units C50 50 100 C25 0 25 75 7 6 5 4 3 2 1 0
ltc6406 6 6406fc typical performance characteristics supply current vs supply voltage supply current vs shdn voltage shutdown supply current vs supply voltage supply voltage (v) 6406 g04 total supply current (ma) v shdn = open 0 2.0 3.5 3.0 0.5 1.0 1.5 2.5 20 15 10 5 0 t a = C40c t a = 0c t a = 25c t a = 70c t a = 85c shdn voltage (v) 6406 g05 v s = 3v 0 2.0 3.0 0.5 1.0 1.5 2.5 t a = C40c t a = 0c t a = 25c t a = 70c t a = 85c total supply current (ma) 20 15 10 5 0 supply voltage (v) 6406 g06 shutdown supply current (a) v shdn = v C 0 2.0 3.5 3.0 0.5 1.0 1.5 2.5 500 450 400 350 300 250 200 150 100 50 0 t a = C40c t a = 0c t a = 25c t a = 70c t a = 85c input noise density vs frequency input noise density vs input common mode voltage differential slew rate vs temperature differential output impedance vs frequency cmrr vs frequency differential psrr vs frequency frequency (hz) input voltage noise density (nv/ hz ) 1k 100k 10m 1m 100 10k 6406 g07 1 10 100 input current noise density (pa/ hz ) 1 10 100 v s = 3v v icm = 1.25v i n e n input common mode voltage (v) 6406 g08 4 3 2 1 0 4 3 2 1 0 0 3.0 2.5 2.0 1.5 1.0 0.5 v s = 3v noise measured at f = 1mhz input voltage noise density (nv/ hz ) input current noise density (pa/ hz ) i n e n temperature (c) 6406 g09 slew rate (v/s) v s = 3v C50 50 100 C25 0 25 75 650 630 610 590 570 550 frequency (mhz) 6406 g10 output impedance () v s = 3v r i = r f = 150 1000 100 10 1 0.01 0.1 1 100 10 1000 2000 frequency (mhz) 6406 g11 cmrr (db) v s = 3v v ocm = 1.25v r i = r f = 150, c f = 1.8pf 0.1% feedback network resistors 80 70 60 5o 10 30 20 40 1 100 10 1000 2000 frequency (mhz) 6406 g12 psrr (db) v s = 3v 80 70 60 5o 10 30 20 40 1 100 10 1000 2000
ltc6406 7 6406fc frequency response vs closed-loop gain frequency response vs load capacitance frequency response vs input common mode voltage typical performance characteristics frequency (mhz) 6406 g16 gain (db) v s = 3v v ocm = v icm = 1.25v r load = 400 50 40 30 20 10 0 C50 C40 C30 C20 C10 a v = 1 a v = 2 a v = 5 a v = 10 a v = 20 a v = 100 1 100 10 1000 2000 a v (v/v) c f (pf) r i () r f () 1 2 5 10 20 100 150 150 150 150 150 150 150 300 750 1.5k 3k 15k 1.8 1.8 0.7 0.3 0.2 0 frequency (mhz) 6406 g17 gain (db) v s = 3v v ocm = v icm = 1.25v r load = 400 r i = r f = 150, c f = 1.8pf capacitor values are from each output to ground. no series resistors are used. 30 20 10 0 C60 C50 C40 C30 C20 C10 c l = 0pf c l = 2pf c l = 3pf c l = 4.7pf c l = 10pf 1 100 10 1000 2000 frequency (mhz) 6406 g18 gain (db) v s = 3v v ocm = 1.25v r load = 400 r i = r f = 150, c f = 1.8pf 10 5 0 C5 C35 C30 C20 C10 C25 C15 v icm = 0v v icm = 0.5v v icm = 1.25v v icm = 2v v icm = 3v 1 100 10 1000 2000 small-signal step response large-signal step response output overdrive response 10ns/div 6406 g13 20mv/div v s = 3v v ocm = v icm = 1.25v r load = 400 r i = r f = 150, c f = 1.8pf c l = 0pf v in = 200mv p-p , differential +out Cout 10ns/div 6406 g14 0.2v/div v s = 3v r load = 400 v in = 2v p-p , differential +out Cout 100ns/div 6406 g15 2.5 2.0 1.5 voltage (v) 1.0 0.5 0 v s = 3v v ocm = 1.25v r load = 200 to ground per output +out Cout (qfn package)
ltc6406 8 6406fc typical performance characteristics harmonic distortion vs frequency harmonic distortion vs input common mode voltage harmonic distortion vs input amplitude harmonic distortion vs frequency harmonic distortion vs input common mode voltage harmonic distortion vs input amplitude intermodulation distortion vs frequency intermodulation distortion vs input common mode voltage intermodulation distortion vs input amplitude frequency (mhz) 6406 g19 distortion (dbc) v s = 3v v ocm = v icm = 1.25v r load = 800 v outdiff = 2v p-p differential inputs C30 C40 C50 C60 C70 C80 C90 C110 C100 2nd, r i = r f = 150 2nd, r i = r f = 500 3rd, r i = r f = 150 3rd, r i = r f = 500 1 100 10 input common mode voltage (v) 6406 g20 distortion (dbc) v s = 3v v ocm = 1.25v f in = 50mhz r load = 800 v outdiff = 2v p-p differential inputs C40 C50 C60 C70 C80 C90 C100 2nd, r i = r f = 150 2nd, r i = r f = 500 3rd, r i = r f = 150 3rd, r i = r f = 500 0 3.0 2.5 2.0 1.5 1.0 0.5 input amplitude (dbm) 6406 g21 distortion (dbc) v s = 3v v ocm = v icm = 1.25v f in = 50mhz r load = 800 r i = r f = 150 differential inputs 2nd 3rd C40 C50 C60 C70 C80 C90 C100 C4 (0.4v p-p ) C2 10 (2v p-p ) 8 6 4 2 0 frequency (mhz) 6406 g22 distortion (dbc) v s = 3v v ocm =v icm = 1.25v r load = 800 v outdiff = 2v p-p single-ended input C30 C40 C50 C60 C70 C80 C90 C110 C100 2nd, r i = r f = 150 2nd, r i = r f = 500 3rd, r i = r f = 150 3rd, r i = r f = 500 1 100 10 input common mode voltage (v) 6406 g23 distortion (dbc) v s = 3v v ocm = 1.25v f in = 50mhz r load = 800 r i = r f = 500 v outdiff = 2v p-p single-ended input C40 C50 C60 C70 C80 C90 C100 0 3.0 2.5 2.0 1.5 1.0 0.5 2nd 3rd input amplitude (dbm) 6406 g24 distortion (dbc) v s = 3v v ocm = v icm = 1.25v f in = 50mhz r load = 800 r i = r f = 500 single-ended input 2nd 3rd C40 C50 C60 C70 C80 C90 C100 C2 8 6 4 2 0 C4 (0.4v p-p ) 10 (2v p-p ) frequency (mhz) 6406 g25 third order imd (dbc) v s = 3v v ocm = v icm = 1.25v r load = 800 r i = r f = 150 2 tones, 1mhz tone spacing, 2v p-p composite differential inputs C30 C40 C50 C60 C70 C80 C90 C110 C100 1 100 10 input common mode voltage (v) 6406 g26 third order imd (dbc) C40 C50 C60 C70 C80 C90 C100 0 3.0 2.5 2.0 1.5 1.0 0.5 v s = 3v v ocm = 1.25v f in = 50mhz r load = 800 r i = r f = 150 2 tones, 1mhz tone spacing, 2v p-p composite differential inputs input amplitude (dbm) 6406 g27 third order imd (dbc) C40 C50 C60 C70 C80 C90 C100 C2 8 6 4 2 0 v s = 3v v ocm = v icm = 1.25v f in = 50mhz r load = 800 r i = r f = 150 2 tones, 1mhz tone spacing differential inputs C4 (0.4v p-p ) 10 (2v p-p ) (qfn package)
ltc6406 9 6406fc typical performance characteristics (msop package) frequency response vs closed-loop gain frequency response vs load capacitance frequency response vs input common mode voltage harmonic distortion vs frequency harmonic distortion vs input common mode voltage harmonic distortion vs input amplitude frequency (mhz) gain (db) 6406 g28 50 40 30 20 10 0 C40 C30 C20 C10 C50 1 100 1000 2000 10 v s = 3v v ocm = v icm = 1.25v r load = 400 a v = 1 a v = 2 a v = 5 a v = 10 a v = 20 a v = 100 a v (v/v) c f (pf) r i () r f () 1 2 5 10 20 100 150 150 150 150 150 150 150 300 750 1.5k 3k 15k 2.2 2.2 0.9 0.4 0.2 0 frequency (mhz) gain (db) 6406 g29 30 20 10 0 C10 C50 C40 C30 C20 C60 1 100 1000 2000 10 v s = 3v v ocm = v icm = 1.25v r load = 400 r i = r f = 150, c f = 2.2pf capacitor values are from each output to ground. no series resistors are used. c l = 0pf c l = 2pf c l = 3pf c l = 4.7pf c l = 10pf frequency (mhz) gain (db) 6406 g30 10 5 0 C5 C10 C30 C25 C20 C15 C35 1 100 1000 2000 10 v s = 3v v ocm = 1.25v r load = 400 r i = r f = 150, c f = 2.2pf v icm = 0v v icm = 0.5v v icm = 1.25v v icm = 2v v icm = 3v frequency (mhz) distortion (dbc) 6406 g31 C30 C40 C50 C60 C70 C80 C90 C100 C110 10 10 100 v s = 3v v ocm = v icm = 1.25v r load = 800 v outdiff = 2v p-p differential inputs 2nd, r i = r f = 150 2nd, r i = r f = 500 3rd, r i = r f = 150 3rd, r i = r f = 500 input common mode voltage (v) 6406 g32 distortion (dbc) C40 C50 C60 C70 C80 C90 C100 0 3.0 2.5 2.0 1.5 1.0 0.5 v s = 3v v ocm = 1.25v f in = 50mhz r load = 800 v outdiff = 2v p-p differential inputs 2nd, r i = r f = 150 2nd, r i = r f = 500 3rd, r i = r f = 150 3rd, r i = r f = 500 input amplitude (dbm) 6406 g33 distortion (dbc) C40 C50 C60 C70 C80 C90 C100 C4 10 8 6 4 2 0 C2 v s = 3v v ocm = v icm = 1.25v f in = 50mhz r load = 800 r i = r f = 150 differential inputs 2nd 3rd (0.4v p-p ) (2v p-p )
ltc6406 10 6406fc shdn (pin 1/pin 7): when shdn is ? oating or directly tied to v + , the ltc6406 is in the normal (active) operat- ing mode. when the shdn pin is connected to v C , the ltc6406 enters into a low power shutdown state with hi-z outputs. v + , v C (pins 2, 10, 11 and pins 3, 9, 12/pins 3, 6): power supply pins. it is critical that close attention be paid to supply bypassing. for single supply applications it is recommended that a high quality 0.1f surface mount ceramic bypass capacitor be placed between v + and v C with direct short connections. in addition, v C should be tied directly to a low impedance ground plane with minimal routing. for dual (split) power supplies, it is recommended that additional high quality, 0.1f ceramic capacitors are used to bypass v + to ground and v C to ground, again with minimal routing. for driving large loads (<200 ), additional bypass capacitance may be needed for optimal performance. keep in mind that small geometry (e.g. 0603 or smaller) surface mount ceramic capacitors have a much higher self resonant frequency than do leaded capacitors, and perform best in high speed applications. v ocm (pin 4/pin 2): output common mode reference voltage. the voltage on v ocm sets the output common mode voltage level (which is de? ned as the average of the voltages on the +out and Cout pins). the v ocm voltage is internally set by a resistive divider between the supplies, developing a default voltage potential of 1.25v with a 3v supply. the v ocm pin can be overdriven by an external voltage capable of driving the 18k thevenin equivalent impedance presented by the pin. the v ocm pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01f, to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the ic. v tip (pin 5/na): this pin can normally be left ? oating. it determines which pair of input transistors (npn or pnp or both) is sensing the input signal. the v tip pin is set by an internal resistive divider between the supplies, developing a default 1.55v voltage with a 3v supply. v tip has a thevenin equivalent resistance of approximately 15k and can be overdriven by an external voltage. the v tip pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01f. see the applications information section for more details. +out, Cout (pins 7, 14/pins 4, 5): un? ltered output pins. besides driving the feedback network, each pin can drive an additional 50 to ground with typical short- circuit current limiting of 55ma. each ampli? er output (qfn/msop) typical performance characteristics (msop package) pin functions harmonic distortion vs frequency harmonic distortion vs input common mode voltage harmonic distortion vs input amplitude frequency (mhz) distortion (dbc) 6406 g34 C30 C40 C50 C60 C70 C80 C90 C100 C110 10 10 100 v s = 3v v ocm = v icm = 1.25v r load = 800 v outdiff = 2v p-p single-ended input 2nd, r i = r f = 150 2nd, r i = r f = 500 3rd, r i = r f = 150 3rd, r i = r f = 500 input common mode voltage (v) 6406 g35 distortion (dbc) C40 C50 C60 C70 C80 C90 C100 0 3.0 2.5 2.0 1.5 1.0 0.5 2nd 3rd v s = 3v v ocm = 1.25v f in = 50mhz r load = 800 r i = r f = 500 v outdiff = 2v p-p single-ended input input amplitude (dbm) 6406 g36 distortion (dbc) C40 C50 C60 C70 C80 C90 C100 C4 10 8 6 4 2 0 C2 v s = 3v v ocm = v icm =1.25v f in = 50mhz r load = 800 r i = r f = 500 single-ended input 2nd 3rd (0.4v p-p ) (2v p-p )
ltc6406 11 6406fc pin functions ltc6406 block diagram/pinout in qfn package v + 100k v + 50 1.25pf 1.25pf 1.25pf 50 v C v + v C C + 1 5 v tip 6 Cin 7 +out 8 +outf 16 nc 15 +in 14 Cout 13 Coutf 2 v + 3 v C v + v + v + v C 4 v ocm 12 v C 6406 bd02 11 v + 10 v + 9 v C v + v C v C v C shdn 43k 30k 30k 32k ltc6406 block diagram/pinout in msop package v + v + v C v + v C C + 1 Cin 2 v ocm 3 v + v + 4 +out 8 +in 7 6 v C v C 5 Cout 43k 30k 6406 bd01 100k shdn is designed to drive a load capacitance of 5pf. larger capacitive loads should be decoupled with at least 15 resistors from each output. +outf, Coutf (pins 8, 13/na): filtered output pins. these pins have a series rc network (r = 50 , c = 3.75pf) con- nected between the ? ltered and un? ltered outputs. see the applications information section for more details. +in, Cin (pins 15, 6/pins 8, 1): noninverting and inverting input pins of the ampli? er, respectively. for best perfor- block diagrams (qfn/msop) mance, it is highly recommended that stray capacitance be kept to an absolute minimum by keeping printed circuit connections as short as possible. nc (pin 16/na): no connection. this pin is not connected internally. exposed pad (pin 17/pin 9): tie the bottom pad to v C . if split supplies are used, do not tie the pad to ground.
ltc6406 12 6406fc applications information figure 1. dc test circuit C + 1 shdn 5 6 Cin 7 +out 8 +outf 16 15 +in v tip nc 14 Cout 100k 13 Coutf v Coutf r f c f v +outf v Cout v +out 2 v + 3 v C v + v + v C v + v C 4 v ocm v shdn v vocm v ocm 12 v C v C 11 v + 10 v + 9 v C v C v C v C c f v C v C 6406 f01 ltc6406 shdn 0.1f 0.01f v cm r f r i r i r bal 100k r bal 100k + C v inp C + v inm v Cin v +in v outcm v + 0.1f 0.1f 0.1f 0.1f 1.25pf 1.25pf 1.25pf 0.1f 0.01f 50 50 functional description the ltc6406 is a small outline, wideband, low noise, and low distortion fully-differential ampli? er with accurate output phase balancing. the ltc6406 is optimized to drive low voltage, single-supply, differential input analog- to-digital converters (adcs). the ltc6406 input common mode range is rail-to-rail, while the output common mode voltage is independently adjustable by applying a voltage on the v ocm pin. the output voltage swing extends from near ground to 2v, to be compatible with a wide range of adc converter input requirements. this makes the ltc6406 ideal for level-shifting signals with a wide common mode range for driving 12-bit to 16-bit single supply, differential input adcs. the differential output allows for twice the signal swing in low voltage systems when compared to single-ended output ampli? ers. the balanced differential nature of the ampli? er also provides even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). the ltc6406 can be used as a single-ended input to differential output ampli? er, or as a differential input to differential output ampli? er. the ltc6406 output common mode voltage, de? ned as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by applying a voltage on the v ocm pin. if the pin is left open, there is an internal resistive voltage divider, which develops a potential of 1.25v (if the supply is 3v). it is recommended that a high quality ceramic capacitor is used to bypass the v ocm pin to a low impedance ground plane. the ltc6406s internal common mode feedback path forces accurate
ltc6406 13 6406fc applications information figure 2. ac test circuit (C3db bw testing) 0.01f C + 1 shdn 5 6 7 8 16 15 nc 14 13 2 v + 3 v C v + v C v + v C 4 v ocm v shdn v vocm v ocm 12 v C v C 11 v + 10 v + 9 v C v C v C v C v C v C 6406 f02 ltc6406 shdn 0.1f 0.01f r t chosen so that r t ||r i = 100 0.1f 0.1f 0.1f 0.1f r i r i 100 100 r t 50 mini-circuits tcm4-19 mini-circuits tcm4-19 v +out v Cout v + 0.1f 0.1f 0.1f 0.1f 0.1f + C v in ? ? 50 ? ? v tip r t Cin +out +outf +in Cout 100k Coutf v Coutf r f c f v +outf v + c f r f 1.25pf 1.25pf 1.25pf 50 50 v Cin v +in output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the v ocm pin. v outcm = v ocm = v + out + v ?out 2 the outputs (+out and Cout) of the ltc6406 are capable of swinging from close to ground to typically 1v below v + . they can source or sink up to approximately 55ma of current. each output is designed to directly drive up to 5pf to ground. higher load capacitances should be decoupled with at least 15 of series resistance from each output. input pin protection the ltc6406 input stage is protected against differential input voltages which exceed 1.4v by two pairs of series diodes connected back to back between +in and Cin. in addition, the input pins have clamping diodes to either power supply. if the input pins are over-driven, the current should be limited to under 10ma to prevent damage to the ic. the ltc6406 also has clamping diodes to either power supply on the v ocm , v tip and shdn pins and if driven to voltages which exceed either supply, they too, should be current limited to under 10ma. shdn pin the shdn pin is a cmos logic input with a 100k internal pull-up resistor. if the pin is driven low, the ltc6406 powers down with hi-z outputs. if the pin is left unconnected or driven high, the part is in normal active operation. some care should be taken to control leakage currents at this pin to prevent inadvertently putting the ltc6406 into shutdown. the turn-on and turn-off time between the shutdown and active states are typically less than 1s.
ltc6406 14 6406fc applications information general ampli? er applications as levels of integration have increased and correspond- ingly, system supply voltages decreased, there has been a need for adcs to process signals differentially in order to maintain good signal to noise ratios. these adcs are typically supplied from a single supply voltage which can be as low as 3v, and will have an optimal common mode input range of 1.25v or 1.5v. the ltc6406 makes interfac- ing to these adcs easy, by providing both single-ended to differential conversion as well as common mode level shifting. the front page of this data sheet shows a typical application. the gain to v outdiff from v inm and v inp is: v outdiff = v + out ?v ?out r f r i ?v inp ?v inm () note from the above equation, the differential output volt- age (v +out C v Cout ) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. this makes the ltc6406 ideally suited for preampli? cation, level shifting and conversion of single-ended signals to differential output signals in preparation for driving differential input adcs. effects of resistor pair mismatch figure 3 shows a circuit diagram which takes into consid- eration that real world resistors will not match perfectly. assuming in? nite open-loop gain, the differential output relationship is given by the equation: v outdiff = v + out ?v ?out ? r f r i ?v indiff + ? avg ?v icm ? ? avg ?v ocm where: r f is the average of r f1 , and r f2 , and r i is the average of r i1 , and r i2 . avg is de? ned as the average feedback factor from the outputs to their respective inputs: avg = 1 2 ? r i1 r i1 + r f1 + r i2 r i2 + r f2 ? ? ? ? ? ? ? is de? ned as the difference in feedback factors: ? = r i2 r i2 + r f2 ? r i1 r i1 + r f1 v icm is de? ned as the average of the two input voltages v inp , and v inm (also called the input common mode voltage): v icm = 1 2 ?v inp + v inm () and v indiff is de? ned as the difference of the input voltages: v indiff = v inp C v inm v ocm is de? ned as the average of the two output voltages v +out and v Cout : v ocm = v + out + v ?out 2 when the feedback ratios mismatch ( ? ), common mode to differential conversion occurs. setting the differential input to zero (v indiff = 0), the de- gree of common mode to differential conversion is given by the equation: v outdiff = v + out ?v ?out v icm ?v ocm () ? ? avg figure 3. real-world application with feedback resistor pair mismatch C + r f2 v Cout v +out v vocm v ocm 6406 f03 r f1 r i2 r i1 + C v inp C + v inm v Cin v +in
ltc6406 15 6406fc applications information in general, the degree of feedback pair mismatch is a source of common mode to differential conversion of both signals and noise. using 1% resistors or better will mitigate most problems, and will provide about 34db worst case of common mode rejection. using 0.1% resistors will provide about 54db of common mode rejection. a low impedance ground plane should be used as a reference for both the input signal source and the v ocm pin. bypassing the v ocm with a high quality 0.1f ceramic capacitor to this ground plane will further help prevent common mode signals from being converted to differential signals. there may be concern on how feedback factor mismatch affects distortion. feedback factor mismatch from using 1% resistors or better, has a negligible effect on distortion. however, in single supply level-shifting applications where there is a voltage difference between the input common mode voltage and the output common mode voltage, resistor mismatch can make the apparent voltage offset of the ampli? er appear worse than speci? ed. the apparent input referred offset induced by feedback factor mismatch is derived from the above equation: v osdiff(apparent) (v icm C v ocm ) ? ? using the ltc6406 in a single supply application on a single 3v supply with 1% resistors, and the input com- mon mode grounded, with the v ocm pin biased at 1.25v, the worst case dc offset can induce 12.5mv of apparent offset voltage. with 0.1% resistors, the worst-case ap- parent offset reduces to 1.25mv. input impedance and loading effects the input impedance looking into the v inp or v inm input of figure 1 depends on whether or not the sources v inp and v inm are fully differential or not. for balanced input sources (v inp = Cv inm ), the input impedance seen at either input is simply: r inp = r inm = r i for single-ended inputs, because of the signal imbalance at the input, the input impedance actually increases over the balanced differential case. the input impedance looking into either input is: r inp = r inm = r i 1? 1 2 ? r f r i + r f ? ? ? ? ? ? ? ? ? ? ? ? input signal sources with non-zero output impedances can also cause feedback imbalance between the pair of feedback networks. for the best performance, it is rec- ommended that the input source output impedance be compensated for. if input impedance matching is required by the source, a termination resistor r1 should be chosen (see figure 4): r1 = r inm ?r s r inm ?r s figure 4. optimal compensation for signal source impedance v s + C C + r f r f r i r inm r s r i r2 r s ||r1 r1 chosen so that r1||r inm = r s r2 chosen to balance r1||r s r1 6406 f04 according to figure 4, the input impedance looking into the differential amp (r inm ) re? ects the single-ended source case, thus: r inm = r i 1? 1 2 ? r f r i + r f ? ? ? ? ? ? ? ? ? ? ? ? r2 is chosen to equal r1||r s : r2 = r1? r s r1 + r s
ltc6406 16 6406fc C + r f v Cout v +out v vocm v ocm 6406 f05 r f r i r i + C v inp + C v cm C + v inm v Cin v +in applications information input common mode voltage range the ltc6406s input common mode voltage (v icm ) is de? ned as the average of the two input voltages, v +in , and v Cin . at the inputs to the actual op amp, the range extends from v C to v + . this makes it easy to interface to a wide range of common mode signals, from ground referenced to v cc referenced signals. moreover, due to external resistive divider action of the gain and feedback resistors, the effective range of signals that can be processed is even wider. the input common mode range at the op amp inputs depends on the circuit con? guration (gain), v ocm and v cm (refer to figure 5). for fully differential input applications, where v inp = Cv inm , the common mode input is approximately: v icm = v + in + v ?in 2 v ocm ? r i r i + r f ? ? ? ? ? ? + v cm ? r f r f + r i ? ? ? ? ? ? with single-ended inputs, there is an input signal compo- nent to the input common mode voltage. applying only v inp (setting v inm to zero), the input common voltage is approximately: v icm = v + in + v ?in 2 v ocm ? r i r i + r f ? ? ? ? ? ? + v cm ? r f r f + r i ? ? ? ? ? ? + v inp 2 ? r f r f + r i ? ? ? ? ? ? use the equations above to check that the v icm at the op amp inputs is within range (v C to v + ). figure 5. circuit for common mode range manipulating the rail-to-rail input stage with v tip to achieve rail-to-rail input operation, the ltc6406 features an npn input stage in parallel with a pnp input stage. when the input common mode voltage is near v + , the npns are active while the pnps are off. when the input common mode is near v C , the pnps are active while the npns are off. at some range in the middle, both input stages are active. this hand-off operation happens automatically. in the qfn package, a special pin, v tip , is made available that can be used to manipulate the hand-off operation between the npn and pnp input stages. by default, the v tip pin is internally biased by an internal resistive divider between the supplies, developing a default 1.55v voltage with a 3v supply. if desired, v tip can be overdriven by an external voltage (the thevenin equivalent resistance is approximately 15k). if v tip is pulled closer to v C , the range over which the npn input pair remains active is increased, while the range over which the pnp input pair is active is reduced. in applica- tions where the input common mode does not come close to v C , this mode can be used to further improve linearity beyond the speci? ed performance. if v tip is pulled closer to v + , the range over which the pnp input pair remains active is increased, while the range over which the npn input pair is active is reduced. in applica- tions where the input common mode does not come close to v + , this mode can be used to further improve linearity beyond the speci? ed performance.
ltc6406 17 6406fc output common mode voltage range the output common mode voltage is de? ned as the aver- age of the two outputs: v outcm = v ocm = v + out + v ?out 2 the v ocm pin sets this average by an internal common mode feedback loop which internally forces v outcm = v ocm . the output common mode range extends from 0.5v above v C to 1v below v + . the v ocm voltage is internally set by a resistive divider between the supplies, develop- ing a default voltage potential of 1.25v with a 3v supply. in single supply applications, where the ltc6406 is used to interface to an adc, the optimal common mode input range to the adc is often determined by the adcs refer- ence. if the adc makes a reference available for setting the input common mode voltage, it can be directly tied to the v ocm pin (as long as it is able to drive the 18k thevenin equivalent input impedance presented by the v ocm pin). the v ocm pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01f to ? lter any common mode noise rather than being converted to dif- ferential noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals by impedance mismatches both externally and internally to the ic. output filter considerations and use filtering at the output of the ltc6406 is often desired to provide antialiasing or to improve signal to noise ratio. to simplify this ? ltering, the ltc6406 in the qfn package includes an additional pair of differential outputs (+outf and Coutf) which incorporate an internal lowpass rc network with a C3db bandwidth of 850mhz (figure 6). these pins each have an output resistance of 50 (toler- ance 12%). internal capacitances are 1.25pf (tolerance 15%) to v C on each ? ltered output, plus an additional applications information 1.25pf (tolerance 15%) capacitor connected between the two ? ltered outputs. this resistor/capacitor combination creates ? ltered outputs that look like a series 50 resistor with a 3.75pf capacitor shunting each ? ltered output to ac ground, providing a C3db bandwidth of 850mhz, and a noise bandwidth of 1335mhz. the ? lter cutoff frequency is easily modi? ed with just a few external components. to increase the cutoff frequency, simply add two equal value resistors, one between +out and +outf and the other between Cout and Coutf (figure 7). these resistors, in parallel with the internal 50 resistors, lower the overall resistance and therefore increase ? lter bandwidth. for example, to double the ? lter bandwidth, add two external 50 resistors to lower the series ? lter resistance to 25 . the 3.75pf of capacitance remains unchanged, so ? lter bandwidth doubles. keep in mind, the series resistance also serves to decouple the outputs from load capacitance. the outputs of the ltc6406 are designed to drive 5pf to ground, so care should be taken to not lower the effec- tive impedance between +out and +outf or Cout and Coutf below 15 . to decrease ? lter bandwidth, add two external capacitors, one from +outf to ground, and the other from Coutf to ground. a single differential capacitor connected between +outf and Coutf can also be used, but since it is being figure 6. ltc6406 internal filter topology C + 7 +out 8 +outf 14 Cout 13 Coutf +outf Coutf 1.25pf 1.25pf 50 50 1.25pf 12 v C 9 v C v C v C 6406 f06 ltc6406 filtered output
ltc6406 18 6406fc applications information driven differentially it will appear at each ? ltered output as a single-ended capacitance of twice the value. to halve the ? lter bandwidth, for example, two 3.9pf capacitors could be added (one from each ? ltered output to ground). alternatively, one 1.8pf capacitor could be added between the ? ltered outputs, which also halves the ? lter bandwidth. combinations of capacitors could be used as well; a three capacitor solution of 1.2pf from each ? ltered output to ground plus a 1.2pf capacitor between the ? ltered outputs would also halve the ? lter bandwidth (figure 8). figure 7. ltc6406 filter topology modi? ed for 2x filter bandwidth (two external resistors) figure 8. ltc6406 filter topology modi? ed for 1/2x filter bandwidth (three external capacitors) C + 7 8 14 13 12 v C 9 v C v C v C 6406 f07 ltc6406 filtered output (1.7ghz) +outf Coutf 49.9 49.9 1.25pf 1.25pf 50 50 1.25pf +out +outf Cout Coutf C + 7 8 14 13 12 v C 9 v C v C v C 6406 f08 ltc6406 filtered output (425mhz) 1.25pf 1.25pf 50 50 1.25pf 1.2pf 1.2pf 1.2pf +outf Coutf +out +outf Cout Coutf
ltc6406 19 6406fc figure 9. noise model of the ltc6406 figure 10. ltc6406 output spot noise vs spot noise contributed by feedback network alone applications information noise considerations the ltc6406s input referred voltage noise is 1.6nv/ hz . its input referred current noise is 2.5pa / hz . in addition to the noise generated by the ampli? er, the surrounding feedback resistors also contribute noise. a noise model is shown in figure 9. the output noise generated by both the ampli? er and the feedback components is governed by the equation: e no = e ni ?1 + r f r i ? ? ? ? ? ? ? ? ? ? ? ? 2 + 2? i n ?r f () 2 + 2? e nri ? r f r i ? ? ? ? ? ? ? ? ? ? ? ? 2 + 2?e nrf 2 a plot of this equation, and a plot of the noise generated by the feedback components for the ltc6406 is shown in figure 10. C + e no 2 r f v ocm e nri 2 r f r i r i e nrf 2 e nri 2 e ncm 2 e ni 2 e nrf 2 i n +2 i n C2 6406 f09 r i = r f () 10 0.1 nv/ hz 1 10 100 100 1k 10k 6406 f10 feedback network noise alone total (amplifier and feedback network) output noise the ltc6406s input referred voltage noise contributes the equivalent noise of a 155 resistor. when the feedback network is comprised of resistors whose values are less than this, the ltc6406s output noise is voltage noise dominant (see figure 10): e no e ni ?1 + r f r i ? ? ? ? ? ? feedback networks consisting of resistors with values greater than about 200 will result in output noise which is resistor noise and ampli? er current noise dominant. e no 2 ?i n ?r f () 2 + 1 + r f r i ? ? ? ? ? ? ?4?k?t?r f lower resistor values (<100 ) always result in lower noise at the penalty of increased distortion due to increased load- ing of the feedback network on the output. higher resistor values (but still less than <500 ) will result in higher output noise, but typically improved distortion due to less loading on the output. the optimal feedback resistance for the ltc6406 runs in between 100 to 500 . the differential ? ltered outputs +outf and Coutf will have a little higher noise than the un? ltered outputs (due to the two 50 resistors which contribute 0.9nv/ hz each), but can provide superior signal-to-noise due to the output noise ? ltering.
ltc6406 20 6406fc layout considerations because the ltc6406 is a very high speed ampli? er, it is sensitive to both stray capacitance and stray inductance. in the qfn package, three pairs of power supply pins are provided to keep the power supply inductance as low as possible to prevent any degradation of ampli? er 2nd harmonic performance. it is critical that close attention be paid to supply bypassing. for single supply applications it is recommended that high quality 0.1f surface mount ceramic bypass capacitor be placed directly between each v + and v C pin with direct short connections. the v C pins should be tied directly to a low impedance ground plane with minimal routing. for dual (split) power supplies, it is recommended that additional high quality, 0.1f ceramic capacitors are used to bypass v + to ground and v C to ground, again with minimal routing. for driving large loads (<200 ), additional bypass capacitance may be needed for optimal performance. keep in mind that small geometry (e.g. 0603) surface mount ceramic capacitors have a much higher self resonant frequency than do leaded capacitors, and perform best in high speed applications. any stray parasitic capacitances to ground at the summing junctions, +in and Cin, should be minimized. this becomes especially true when the feedback resistor network uses resistor values >500 in circuits with r f = r i . excessive peaking in the frequency response can be mitigated by adding small amounts of feedback capacitance around r f . always keep in mind the differential nature of the ltc6406, and that it is critical that the load impedances seen by both outputs (stray or intended), should be as balanced and symmetric as possible. this will help preserve the natural balance of the ltc6406, which minimizes the generation of even order harmonics, and improves the rejection of common mode signals and noise. it is highly recommended that the v ocm pin be bypassed to ground with a high quality ceramic capacitor whose value exceeds 0.01f. this will help stabilize the common mode feedback loop as well as prevent thermal noise from the internal voltage divider and other external sources of noise from being converted to differential noise due to divider mismatches in the feedback networks. it is also recommended that the resistive feedback networks be comprised of 1% resistors (or better) to enhance the output common mode rejection. this will also prevent v ocm input referred common mode noise of the common mode ampli? er path (which cannot be ? ltered) from being converted to differential noise, degrading the differential noise performance. feedback factor mismatch has a weak effect on distortion. using 1% or better resistors will limit any mismatch from impacting ampli? er linearity. however, in single supply level-shifting applications where there is a voltage differ- ence between the input common mode voltage and the output common mode voltage, resistor mismatch can make the apparent voltage offset of the ampli? er appear worse than speci? ed. interfacing the ltc6406 to a/d converters rail-to-rail input and fast settling time make the ltc6406 ideal for interfacing to low voltage, single supply, differ- ential input adcs. the sampling process of adcs create a sampling glitch caused by switching in the sampling capacitor on the adc front end which momentarily shorts the output of the ampli? er as charge is transferred between the ampli? er and the sampling capacitor. the ampli? er must recover and settle from this load transient before this acquisition period ends for a valid representation of the input signal. in general, the ltc6406 will settle much more quickly from these periodic load impulses than from a 2v input step, but it is a good idea to either use the ? ltered outputs to drive the adc (figure 11 shows an example of this), or to place a discrete r-c ? lter network between the differential un? ltered outputs of the ltc6406 and the input of the adc to help absorb the charge injection that comes out of the adc from the sampling process. the capacitance of the ? lter network serves as a charge reservoir to provide high frequency charging during the sampling process, while the two resistors of the ? lter network are used to dampen and attenuate any charge kickback from the adc. the selection of the r-c time constant is trial and error for a given adc, but the following guidelines are recommended: choosing too large of a resistor in the decoupling network leaving insuf? cient settling time will create a voltage divider between the dynamic input imped- ance of the adc and the decoupling resistors. choosing too small of a resistor will possibly prevent the resistor applications information
ltc6406 21 6406fc figure 11. interfacing the ltc6406 to an adc 0.1f C + 1 shdn 5 6 Cin 7 +out 8 +outf 16 15 +in nc 14 Cout 13 Coutf +ina Cina 150 2 v + 3 v C v + v + v C 3.3v v ocm v ocm 12 v C 11 v + 10 v + 9 v C v C v C 6406 f11 ltc6406 ltc2208 v in , 2v p-p shdn 150 150 150 0.1f 3.3v 4 0.1f 0.1f control gnd v dd d15 ? ? d0 0.1f v cm 2.2f 3.3v 1f 1f v tip 100k 1.8pf 1.8pf 1.25pf 1.25pf 1.25pf 50 50 applications information from properly dampening the load transient caused by the sampling process, prolonging the time required for settling. in 16-bit applications, this will typically require a minimum of 11 r-c time constants. it is recommended that the capacitor chosen have a high quality dielectric (such as c0g multilayer ceramic). typical application dc-coupled level shifting of demodulator output ltc2249 14-bit adc 80mhz sample clock 3.3v 6406 ta02 10dbm r9 10 c8 22pf c7 22pf c6 22pf c2 10pf c1 10pf rf in 900mhz C3dbm c3 12pf r10 10 r7 49.9 r5 475 r6 475 c5 1.8pf c4 1.8pf diff output z 130 \\ 2.5pf dc level 1.25v dc level 3.9v dc level 3.3v gain: 10db input nf: 18db oip3: 44dbm see dn418 for more information gain: 3db input nf: 13db oip3: 31dbm r8 49.9 r3 75 r4 75 r1 75 r2 75 0dbm identical q channel 5v 5pf 65 5pf 65 C + + C 3.3v ltc6406 v ocm 1.25v 5v i 5v 5pf 65 5pf 65 5v q 5v lt5575
ltc6406 22 6406fc ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) package description 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16) qfn 0904 0.25 0.05 0.50 bsc package outline
ltc6406 23 6406fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ms8e package 8-lead plastic msop (reference ltc dwg # 05-08-1662) msop (ms8e) 0307 rev d 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 8 1 bottom view of exposed pad option 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc 0.1016 0.0508 (.004 .002)
ltc6406 24 6406fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0609 rev c ? printed in usa ltc2207 3.3v 6406 ta03 r1 51.1 p 5v sine wave (10v p-p ) centered at 0v r2 51.1 r3, 100 r4, 100 c1, 2.7pf c2, 2.7pf 2v p-p diff output level-shifted to 1.25v v in r5 511 r6 511 + C C + 3.3v ltc6406 v cm = 1.25v typical applications part number description comments lt1809/lt1810 single/dual 180mhz, 350v/s rail-to-rail input and output low distortion op amps 180mhz, 350v/s slew rate, shutdown lt1993-2/lt1993-4/ lt1993-10 800mhz/900mhz/700mhz low distortion, low noise differential ampli? er/adc driver a v = 2v/v / a v = 4v/ v / a v = 10v/v, nf = 12.3db/14.5db/12.7db, oip3 = 38dbm/40dbm/40dbm at 70mhz lt1994 low noise, low distortion fully differential input/output ampli? er/driver low distortion, 2v p-p , 1mhz: C94dbc, 13ma, low noise: 3nv/ hz ltc6400-20 1.8ghz low noise, low distortion, differential adc driver 300mhz if ampli? er, a v = 20db ltc6401-20 1.3ghz low noise, low distortion, differential adc driver 140mhz if ampli? er, a v = 20db lt6402-6/lt6402-12/ lt6402-20 300mhz/300mhz/300mhz low distortion, low noise differential ampli? er/adc driver a v = 6db/a v = 12db/a v = 20db, nf = 18.6db/15db/12.4db, oip3 = 49dbm/43dbm/51dbm at 20mhz ltc6404-1 600mhz low noise, low distortion, differential adc driver 1.5nv/ hz noise, C90dbc distortion at 10mhz lt6600-2.5/lt6600-5/ lt6600-10/lt6600-20 very low noise, fully differential ampli? er and 4th order filter 2.5mhz/5mhz/10mhz/20mhz integrated filter, 3v supply, so-8 package attenuating and level shifting a single-ended 5v signal to a differential 2v p-p signal at a 1.25v common mode related parts second order 30mhz 0.5db chebyshev differential input/output lowpass filter ltc2207 105mhz clock 3.3v 6406 ta04 r9 4.99 c7 4.7pf c5 4.7pf c6 4.7pf c3 68pf r10 4.99 r7 51.1 c1, 8.2pf c2 8.2pf v cm r8 51.1 r2 232 r3 150 r1, 150 r6 150 C + + C r4 232 r5 150 c4 68pf + C differential v in ltc6406

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